Digital communications systems and digital storage systems (e.g., hard disk drives) are similar from the perspective of extracting the original (transmitted or stored) bits from the received signal or from the readback signal. In the case of communications channels, the digital information is transferred from one location to another location, but at the same time (perhaps with a small transmission delay), whereas in storage channels, the information is transferred from one time to a later time, but at the same location. The goal in both cases is to retrieve the original bits as accurately as possible in the presence of impairments such as noise and inter-symbol interference (ISI).
One method for improving the accuracy of the retrieved digital information involves using error correcting codes (ECCs). ECCs typically use parity bits to introduce redundancy into the signal prior to transmission or storage. Such redundancy is subsequently used to decode the encoded information. In order to demonstrate the typical manner in which parity bits are currently used for this purpose, an example of a known digital storage system and its operations will be described with reference to FIGS. 1-5.
FIG. 1 illustrates a block diagram of a known digital storage system 1 that uses parity bits to encode information prior to storing the information. The digital storage system 1 includes an encoder 2 that encodes information bits by pseudo-randomly interleaving parity bits throughout the information bits. The encoder 2 is typically a two-dimensional product code (TPC) encoder. The encoded information bits are subsequently read out of the recording channel 3. The recording channel 3 typically includes physical and electrical components (not shown), such as the read/write head, the read/write head armature, the recording media, the pre-amplifier, etc.
As encoded information bits are read out of the recording channel 3, they are processed by a channel detector 4 that performs an algorithm to detect bits. The detector 4 is typically a hard Viterbi detector that produces hard decisions (i.e., a decision that a bit is either a 1 or a 0) or a soft-output Viterbi algorithm (SOVA) detector that produces hard decisions and reliability estimates (i.e., respective estimates as to the reliability of the respective hard decisions). The output of the channel detector 4 is received by a channel decoder 5 that deinterleaves the parity bits and decodes the bit sequence.
For this example, it will be assumed that a particular sequence of original information bits, uk=010110, is to be stored in the recording channel 3. This particular sequence is represented by the 3×2 table 11 shown in FIG. 2A. The sequence is encoded by the encoder 2 to produce a codeword. Assuming that the encoder 2 is a two-dimensional product (TPC) encoder, a parity bit is added to each row and to each column of the 3×2 table 11 to produce an even parity code (i.e., each column and each row contains an even number of 1's). The resulting 4×3 table 12 is shown in FIG. 2B. For this example, it will be assumed that each column in the 4×3 table 12 corresponds to a single parity codeword. However, this is not normally the case. As stated above, the parity bits are typically pseudo-randomly interleaved throughout the original information bits. For ease of explanation, the parity bits are shown as simply added to each row and column of table 11 in such a way that each 4-bit column of table 12 is provided with even parity.
The resulting codeword ck=010111001001 is recorded in the recording channel 3. The signal xk read from the recording channel 3 is typically corrupted by noise, nk, such as additive Gaussian noise, for example, which produces samples yk that are received by the channel detector 4. The channel detector 4, which will be assumed to be a SOVA detector for this example, receives the samples yk and produces hard decisions and corresponding soft reliability estimates. This information is then processed by the decoder 5 to produce the recovered information bits.
The recording channel 3 may be modeled as a very simple partial response one-delay (1-D) element channel, as shown in FIG. 3. The recording channel 3 modeled as a 1-D element channel 20 has an input 21, an output 22, a summer 23 and a delay element 24. The summer 23 sums the bit stored in the delay element 24 with the current bit in the ck sequence to produce a current bit in the output sequence xk.
FIG. 4 illustrates a state trellis diagram 30 for the 1-D element channel 20 shown in FIG. 3. The channel model 20 has two states, namely, state 0 and state 1. The channel states depend on the bit stored in the delay element 24. The initial state of the delay element 24 is presumed to be zero. Each of the transition branches 32-35 in the trellis diagram 30 is associated with one input bit and one output bit. For example, “0/1” corresponds to an input bit 1 and an output bit 0. If the state of the delay element 24 is 0 at time k−1and the channel input bit is 0 at time k−1, then the channel output bit at time k−1 is 0 (i.e., 0+0). Branch 32 of the trellis diagram 30 represents this 0/0output/input. If the channel input bit at time k−1 is 1 and the state of the delay element 24 is 0 at time k−1, then the channel output bit at time k−1 is 1 (i.e., 1-0). Branch 33 of the trellis diagram 30 represents this 1/1 output/input. If the state of delay element 24 at time k−1 is 1 and the channel input at time k−1 is 0, then the channel output at time k−1 is 0. Branch 34 of the trellis diagram 30 represents this −1/0 output/input. If the state of delay element 24 at time k−1 is 1 and the channel input at time k−1 is 1, then the channel output at time k−1 is 0. Branch 35 of the trellis diagram 30 represents this 0/1output/input.
FIG. 5 illustrates the 1-D trellis diagram 40 corresponding to the ideal channel output, xk=01−1100−101−101, for the channel input, ck=010111001001, for times k=0 through k=11 for the entire 12-bit sequence shown in FIG. 3. The sequences ck, xk, nk, and yk for this example are listed below in Table 1.
TABLE 1Sequence valuesk01234567891011ck010111001001xk01−1100−101−101nk000−0.60000.50000.2yk01−10.400−10.51−101.2
The SOVA detector 4 determines the maximum likelihood (ML) path that has the minimum distance to the received sequence yk. Assuming the initial state of the delay element is 0, the ML path is made up of branches 41-52 of the trellis 40 shown in FIG. 5. As is well know in the art, the ML path is chosen by selecting the branches that have ideal inputs that are closest to the values of the corresponding yk samples. For example, for yk=0 at time k=0, the chosen branch is the 0/0 branch labeled 41. For yk=1 at time k=1, the chosen branch is the 1/1 branch labeled 42. For yk=−1 at time k=2, the chosen branch is the −1/0 branch labeled 43.
By continuing to perform this algorithm for times k=3 through k=11, the SOVA detector 4 generates an estimated input bit sequence of 010000001001 for times k=1 through k=11. A comparison of this sequence with the original input sequence ck shown in Table 1 shows that the bit decisions made by the SOVA detector 4 for times k=3, k=4 and k=5 do not have the same values as the bits of the ck sequence for those same times. Therefore, although the SOVA detector 4 is reasonably accurate at detecting bits, there is room for improvement.
Aside from the need to improve data detection accuracy, the configuration described above with reference to FIG. 1 has certain disadvantages. As stated above, the parity bits are typically inserted by the encoder 2 via a pseudo-random bit interleaving process. This process is intended to improve the performance of the system. However, it is possible for the interleaved bit sequence to violate certain modulation constraints imposed by the modulation encoder (not shown), which may further reduce data detection accuracy. Furthermore, the system generally requires an interleaver following the encoder 2 and a de-interleaver following the detector 4, and thus requires additional hardware. In addition, memory buffers are needed in the encoder 2 and in the decoder 5 to store the interleaved and de-interleaved bit sequences, respectively, which presents further difficulties in terms of hardware requirements.
Another known digital recording system, which is shown in FIG. 6, includes a single parity encoder 7, a read channel 8 and a hard Viterbi detector 9 that uses single parity. This system 6 does not include a decoder because a decoder is not necessary. The Viterbi detector with single parity detects and decodes the data. Adding a decoder would not provide any improvement in performance. However, performance of the system 6 is limited by its use of single parity because the use of single parity in the system 6 does not provide sufficient protection against errors. For this reason, the system 1 shown in FIG. 1 has been proposed because the use of interleaved parity bits in two-dimensions provides sufficient protection against errors, although the system 1 has the aforementioned other disadvantages.
Accordingly, a need exists for a data detection and decoding system that detects bits with improved accuracy. A need also exists for a data detection and decoding system that eliminates the need to interleave the parity bits in the encoder and de-interleave the parity bits in the decoder, while still providing improved performance over existing data detection and decoding systems.